The present invention relates generally to network interfacing, and more particularly, to a device and method for interpolating signal samples at a resampled clock phase from sample values at related clock phases.
The transmission of various types of digital data between computers continues to grow in importance. The predominant method of transmitting such digital data includes coding the digital data into a low frequency baseband data signal and modulating the baseband data signal onto a high frequency carrier signal. The high frequency carrier signal is then transmitted across a network cable medium, via RF signal, modulated illumination, or other transmission medium, to a remote computing station.
At the remote computing station, the high frequency carrier signal must be received and demodulated to recover the original baseband data signal. In the absence of any distortion or reflection of the carrier signal across the network medium, the received carrier would be identical in phase, amplitude, and frequency to the transmitted carrier and could be demodulated using known mixing techniques to recover the base data signal. The baseband data signal could then be recovered into digital data using known sampling algorithms.
However, the network topology tends to distort the high frequency carrier. In the case of a network cable transmission medium, numerous branch connections and different lengths of such branches causing numerous reflections of the transmitted carrier. The high frequency carrier is further distorted by spurious noise caused by electrical devices operating in close proximity to the cable medium. Such problems are even more apparent in a network which uses home telephone wiring cables as the network cable medium because the numerous branches and connections are typically designed for transmission of plain old telephone system POTS signals in the 0.3-3.4 kilohertz frequency and are not designed for transmission of high frequency carrier signals on the order of 7 Megahertz. Further yet, the high frequency carrier signal is further distorted by turn-on transients due to on-hook and off-hook noise pulses of the POTS utilizing the network cables.
Such distortion of frequency, amplitude, and phase of the high frequency carrier signal degrades network performance and tends to impede the design of higher data rate networks. Known techniques for compensating for such distortion and improving the data rate of a network include complex modulation schemes and frequency diversity.
Utilizing a complex modulation scheme such as quadrature amplitude modulation (QAM), both the amplitude and phase of the high frequency carrier are modulated to represent I and Q components of a baseband signal. Referring to FIG. 1, a 4-QAM modulation constellation 10 is shown. In operation, each data symbol is represented by an I-value of +1 or xe2x88x921 and a Q-value of +1 or xe2x88x921 such that the data symbol can be represented by one of the four states 12(a)-12(d) in constellation 10. Each constellation point 12(a)-12(d) represents a unique combination of carrier amplitude and phase. For example, constellation point 12(a) represents a carrier amplitude of 14 and a carrier phase 16.
FIG. 2 illustrates the utilization of frequency diversity by transmitting the same data in three mutually exclusive sub-spectra 18(a)-18(c) of the transmission band 20. Therefore, if a portion of the band is distorted (e.g. one or more of the sub-spectra 18(a)-18(c)), the data may still be recovered at the receiver from a less distorted portion of the sub-spectra 18(a)-18(c). For example, a data signal modulated onto a 7 MHz carrier utilizing 6 MHz of bandwidth may include three mutually exclusive sub-bands 18(a)-18(c) centered at 5 MHz, 7 MHz and 9 MHz.
One approach to demodulating and recovering data from such complex signals includes receiver circuits implemented by digital signal processing (DSP).
In accordance with DSP technology, a digital carrier signal is generated by sampling the carrier signal with an A/D converter which is clocked at several times the carrier frequency. Assuming a carrier frequency on the order of 7 MHz, the sampling frequency will be a minimum of 14 MHz in accordance with Nyquist theorem and typically will be on the order of 28 to 32 MHz. A problem associated with processing digital samples at such rates to demodulate a complex modulated carrier, and to process mutually exclusive sub-bands of a frequency diverse system, is that very large and costly digital signal processing systems would be required.
A known solution to reduce the hardware size and complexity is to use decimation filters to reduce the sampling rate after demodulation such that the equalizer filter circuits can be simplified. A problem associated with decimation filters is that they ignore, or decimate, all samples except those in a retained phase which can significantly degrade the quality of the signal represented by the retained samples. Further, when the retained phase is not a phase that closely matches the phase of the transmitted signal, the decimated signal quality is reduced. Therefore, what is needed is a receiver circuit which provides a low frequency sample signal which does not suffer the signal degradation disadvantages associated with known systems.
A first aspect of the present invention is to provide a receiver circuit for recovering data from a modulated carrier signal. The receiver circuit comprises a sampler, such as an A/D converter, receiving the modulated carrier signal and generating a digital carrier signal. The digital carrier signal is represented by a sequence of sample values in accordance with a first sampling frequency clock signal. A first complex mixer frequency shifts the digital carrier signal by a frequency equal to one fourth the first sampling frequency to generate a frequency shifted data signal. The frequency shifted data signal is also a sequence of sample values with a sampling rate at the first sampling frequency. A resampling circuit receives the frequency shifted data signal and generates a resampled signal. The resampled signal comprises a sequence of resample values at a sampling rate less than the first sampling frequency and at a phase independent of the phase of the clock signal.
Each resample value may be calculated, utilizing an interpolation function, as a function of the phase of the resampled signal and sample values comprising the frequency shifted data signal which are closest in phase to the phase of the resampled signal.
A decimation circuit may receive the frequency shifted data signal and generate four decimated signals, each at one of the four phases of the frequency shifted data signal that are closest in phase to the phase of the resampled signal. The resampler then receives the four decimated data signals. Further, a second complex mixer may frequency shift the decimated data signals by a frequency equal to one half of a sampling rate of the decimated signals.
Further yet, a slicer may receive the resampled data signal and map the resampled data signal to defined constellation coordinates to recover transmitted data. The slicer may also generate an error signal representing the difference between the resampled data signal and the defined constellation coordinates.
In the preferred embodiment, the carrier frequency is 7 MHz, the first sampling frequency is 32 MHz, the sampling rate of the decimated signals are 2 MHz, the first complex mixer frequency shifts the digital carrier by 8 Mhz, the sampling rate of each of the decimated signals is 2 MHz, and the second complex mixer frequency shifts the four decimated signals by 1 Mhz.
A second aspect of the present invention is to provide a receiver circuit for recovering data from a modulated carrier signal. The receiver circuit comprises a decimate circuit receiving a data signal at a first sampling rate and receiving a phase signal from a phase selection circuit. The decimation circuit separates the data signal into a plurality of decimated signals each at a unique decimation phase. A resampler receives the plurality of decimated signals and the phase signal and generates a resampled data signal at a resampling phase in accordance with the phase signal. The resampling phase is independent of the phases of the plurality of decimated signals and the resampled data signal is interpolated from at least two of the decimated signals.
The phase selection circuit may provide for at least two of the decimated signals to be those closest in phase to the phase of the resampling phase. In the preferred embodiment, decimation circuit separates the data signal into four decimated signals and the four decimated signals are the four at phases closest to the resampling phase. The resampled data signal is interpolated form the four decimated data signals. Again, the carrier frequency is 7 MHz, the first sampling rate is 32 MHz, the sampling rate of the decimated signals and the resampled data signal are 2 MHz.
A slicer may receive the resampled data signal and map the resampled data signal to defined constellation coordinates to recover transmitted data. The slicer may also generate an error signal representing the difference between the resampled data signal and the defined constellation coordinates. The selection circuit may receive the error signal and calculate a new resampling phase as a function of the existing resampling phase and the error signal. Further, the phase signal may represent an integer phase signal which is provided to the decimation circuit for selecting the four decimation phases closest to the resampling phase and a fractional phase signal which is provided to the resampler for interpolating the resampled data signal from the four decimated data signals.
A third aspect of the present invention is to provide a method of recovering data from a modulated carrier signal. The method comprises: a) sampling the modulated carrier signal in accordance with a clock signal at a first sampling frequency to generate a digital carrier signal; b) frequency shifting the digital carrier signal by a frequency equal to one fourth the first sampling frequency to generate a frequency shifted data signal with a sample frequency equal to the first sampling frequency; and c) generating, from the frequency shifted data signal, a resampled signal comprising a sequence of resample values at a sampling rate less than the first sampling frequency and at a phase independent of the phase of the clock signal.
Each resample value in the resampled signal may be calculated, or interpolated, as a function of the phase of the resampled signal and sample values comprising the frequency shifted data signal which are closest in phase to the phase of the resampled signal.
The method may further include generating four decimated signals from the frequency shifted data signal, each at one of the four phases of the frequency shifted data signal that are closest in phase to the phase of the resampled signal. The resampled signal would then be calculated from the four decimated signals. The four decimated signals may be frequency shifted by a frequency equal to one half of a sampling rate of the decimated signals. Again, in the preferred embodiment, the carrier frequency is 7 MHz, the first sampling frequency is 32 MHz, the sampling rate of the decimated signals are 2 MHz, the frequency shift of the digital carrier signal is by 8 Mhz, the sampling rate of the decimated signals are 2 MHz, and the frequency shift of the four decimated signals is by 1 Mhz.